Intergraph’s Intellectual Property division was created in 2002. It was created as a single independent point of contact for companies interested in licensing Intergraph’s technology. The division’s goal is to license Intergraph’s technology to a number of industries, including computers, consumer electronics, telecommunications, and electronics design.
Intergraph’s Clipper microprocessor is an innovative architecture which brought mainframe-class computing power to low-cost integrated circuit technology. Clipper-related patents define an architecture related to the control of a microprocessor’s cache memory management – keeping cache memory and RAM coherent (in synch) while reducing the number of cache-to-RAM read/write activities. This technique permits up to a 30% gain in microprocessor and/or system performance. Caching is implemented at the processor level and also at the system level over the system bus to improve performance between the processor and main memory. Intergraph’s patents cover both.
Parallel processing – or parallel instruction computing (PIC) – increases the number of calculations that can be done in a certain amount of time by allowing a CPU to execute multiple instructions simultaneously. Intergraph has several patents which define a method for using software to enable parallel instruction computing. The patents cover (1) the techniques used to convey compiler-recognized parallelism to the hardware and (2) a novel approach to routing instructions to any of the parallel processing units.
These patented PIC technologies were developed for Intergraph’s next generation Clipper microprocessor. The original Clipper was based upon a hybrid RISC/CISC superscalar, superpipelined computing architecture. The inventors of the Clipper microprocessor viewed parallel instruction computing as the next logical progression in microprocessor design. Intergraph developed its patented PIC technology in 1992 when the company’s Advanced Processor Division designed its next generation C5 Clipper microprocessor.
Note: Although Intergraph’s PIC technology was developed for the Clipper microprocessor, the so-called “PIC patents” (dealing with parallel instruction computing) are totally different from Intergraph’s so-called “Clipper patents” (which deal with cache memory management).
Intergraph’s High-Availability Super Server (“Super Server”) inventions resolve problems and limitations encountered when combining a rather large number of microprocessors into a clustered server architecture. Specifically, Super Server solves coherency problems among large numbers of microprocessors in large clustered servers. (A cluster is a circuit board containing a number of microprocessors.)
A cache is small, fast memory which holds recently accessed data, designed to speed up subsequent access to the same data. Cache-coherency is the synchronization of data in multiple caches to assure data accuracy and reliability. The cache-coherency in most microprocessors limits a clustered server to no more than eight microprocessors. Super Server permits clusterings well beyond this limit, allowing larger servers to be built more economically.